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Design of Prefix Adders Using Transmission Gate

Language EnglishEnglish
Book Paperback
Book Design of Prefix Adders Using Transmission Gate Nehru Kandasamy
Libristo code: 18732509
Publishers LAP Lambert Academic Publishing, November 2016
The design of 64-bit parallel prefix adder using transmission gate which acquires least number of no... Full description
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The design of 64-bit parallel prefix adder using transmission gate which acquires least number of nodes with the lowest transistor count and low power consumption has been addressed in this book. The 64-bit parallel prefix adder is designed and comparison is made among previous parallel prefix adders. The result shows that the proposed 64-bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the speed. The proposed parallel prefix adders consumes less power and implements lesser number of transistors compared to existing parallel prefix adders.

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About the book

Full name Design of Prefix Adders Using Transmission Gate
Author Nehru Kandasamy, Nagarjuna Telagam
Language English
Binding Book - Paperback
Date of issue 2017
Number of pages 52
EAN 9786202079938
Libristo code 18732509
Publishers LAP Lambert Academic Publishing
Weight 96
Dimensions 150 x 220 x 3

Categories

Technology, Engineering, Agriculture > Energy technology & engineering > Electrical engineering
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