Kontakt
Kako kupovati
Dostava
Savjetnik za kupnju
Cache and Interconnect Architectures in Multiprocessors
Engleski
249 b
Do 30 dana za povrat
Kupci su kupili i
Tvrdi uvez
26.14
€
/
Meki uvez
30.90
€
Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop.
Informacije o knjizi
Engleski
Kategorija
Poklonite ovu knjigu još danas
To je jednostavno
1 Dodajte knjigu u košaricu i odaberite isporuku kao poklon 2 Zauzvrat ćemo vam poslati kupon 3 Knjiga dolazi na adresu poklonoprimcaMoglo bi vas zanimati i
/
Meki uvez
56.03
€
/
Meki uvez
13.06
€
/
Meki uvez
17.42
€
/
Meki uvez
40.33
€
/
Meki uvez
10.33
€
Dobar dan! Ja sam Libroamiko, vaš književni savjetnik.
Kako vam mogu pomoći?