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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Jezik EngleskiEngleski
Knjiga Tvrdi uvez
Knjiga Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs Brandon Noia
Libristo kod: 02076816
Nakladnici Springer International Publishing AG, studeni 2013
This book describes innovative techniques to address the testing needs of 3D stacked integrated circ... Cijeli opis
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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

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Informacije o knjizi

Puni naziv Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Autor Brandon Noia, Krishnendu Chakrabarty
Jezik Engleski
Uvez Knjiga - Tvrdi uvez
Datum izdanja 2013
Broj stranica 245
EAN 9783319023779
ISBN 3319023772
Libristo kod 02076816
Nakladnici Springer International Publishing AG
Težina 514
Dimenzije 157 x 243 x 16

Kategorija

Technology, Engineering, Agriculture > Electronics & communications engineering > Electronics engineering > Electronics: circuits & components
Technology, Engineering, Agriculture > Electronics & communications engineering > Electronics engineering > Electronic devices & materials
Technology, Engineering, Agriculture > Technology: general issues > Engineering: general
Computing & Information Technology > Computer science > Computer architecture & logic design
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