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In-loop Filtering in Emerging HEVC Standard
From Performance Analysis to Hardware Design Implementation
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This book proposes the design and architecture of De-blocking filter (DBF) which removes blocking artifacts in new emerging High Efficiency Video Coding (HEVC). DBF of HEVC employs two type of filter, normal and strong filter. The architecture of both filtering modes is proposed in this book. Distributed memories and two data paths increases the parallelism and make architecture more efficient. The proposed architecture was first implemented in MATLAB 2013®, then described using Verilog in MODELSIM 10.2c® and, was finally synthesized in Xilinx ISE Design Suite 14.5®. The proposed architecture is described by Verilog and implemented on FPGA. The architecture can realize real-time to compute 4k UHD video at 30fps by using 46.65 million clocks. The total equivalent gate count of proposed architecture is 11.4K for Virtex-4 board implementation and 46K for Virtex-5 board.
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