Kontakt
Kako kupovati
Dostava
Savjetnik za kupnju
Logic Synthesis and Verification Algorithms
Engleski
262 b
Do 30 dana za povrat
Moglo bi vas zanimati i
/
Adobe ePub DRM
279.22
€
/
Meki uvez
14.16
€
/
Meki uvez
13.25
€
/
Meki uvez
9.64
€
/
Tvrdi uvez
68.61
€
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. §Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. §A unique feature of this text is the large collection of solved problems. §Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
Informacije o knjizi
Engleski
Kategorija
Poklonite ovu knjigu još danas
To je jednostavno
1 Dodajte knjigu u košaricu i odaberite isporuku kao poklon 2 Zauzvrat ćemo vam poslati kupon 3 Knjiga dolazi na adresu poklonoprimcaDobar dan! Ja sam Libroamiko, vaš književni savjetnik.
Kako vam mogu pomoći?